1. Field of the Invention
This invention generally relates to a semiconductor package and a method for manufacturing the same, and more particularly to a wafer level semiconductor package and a method for manufacturing the same.
2. Description of the Related Art
The semiconductor package provides four functions, i.e. signal distribution, power distribution, heat dissipation and element protection. In general, a semiconductor chip is packaged into an enclosure (e.g. a single-chip module), and then disposed on a printed circuit board, together with other components, such as capacitors, resistors, inductors, filters, switches, and optical and RF components.
The complementary metal oxide semiconductor (CMOS) technology for making optical components is similar to that for making semiconductor chips. CMOS is typically formed by silicon (Si) and germanium (Ge) and generally includes NMOS (negative polarity) and PMOS (positive polarity) transistors. For optical components, NMOS and PMOS can generate currents after sensing light, and the currents are then recorded and read as image.
Further, as the demands for lighter and more complex electronic devices gradually increase, the operating speed and the complexity of IC chips have become higher and higher. Accordingly, a higher packaging efficiency is required. In the prior art, various semiconductor packages and manufacturing methods have been provided for improving the packaging efficiency and reliability. For example, U.S. Pat. No. 6,040,235 entitled “Methods And Apparatus For Producing Integrated Circuit Devices” issued to Badehi on May 21, 2000, and U.S. Pat. No. 6,117,707 entitled “Methods Of Producing Integrated Circuit Devices” issued to Badehi on Sep. 12, 2000 disclose methods for manufacturing the semiconductor packages. However, theses semiconductor packages and the manufacturing methods in the prior art still have many limitations and drawbacks, and therefore can not completely meet the requirements for semiconductor packages.
Accordingly, there exists a need for providing a wafer level semiconductor package to further meet the requirement for semiconductor packages.